Hardware Architectures for DSP Algorithms

Course Description

This course introduces techniques for refining signal processing algorithms to hardware implementations described using a hardware descriptive language. Students design, model and simulate signal processing algorithms through different levels of hardware refinement. Hardware structures for finite impulse filter (FIR), infinite impulse filters (IIR) and adaptive equalizers are studied and analyzed throughout the course. Multi-rate and multi-signal concepts are covered during the course and these concepts are applied to different signal processing techniques. Cut-set retiming methods to generate parallel and systolic array filtering structures are also covered in the course. By the end of the course, students are able to refine a signal processing algorithm targeting hardware platforms such as field programmable gate arrays (FPGA). An understanding of digital signal processing and VHDL for FPGAs is required for this course. Prerequisite(s): 525.627 Digital Signal Processing and 525.642 FPGA Design Using VHDL, or equivalent to each of these courses

Code

EN.525.677

Credits

3

Subject

Electrical and Computer Engineering

Programs That Include This Course

• Master's Electrical and Computer Engineering, Master of Science