Drexel University 3 credits ECEE
Covers digital ICs using CMOS technology. Transistor level building blocks, -NOT, NAND, NOR, XOR, OAI, and AOI ? are designed using industry standard CAD tools, e.g. Cadence. Circuit topologies such as CPL, transmission gates are explored. CMOS technology/fabrication and layout are discussed to optimize speed, power, and area.
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