New York University 3 credits Elect. Engineering - ECE GRAD
This course shows how a hardware-description language (for example, VHDL) can be used for computer hardware modeling, logic synthesis, register-level synthesis and simulation. The resulting design with hundreds or thousands of gates is then ready to be downloaded to form FPGA chips or silicon cells. Programs used: QuickVHDL, modeling and simulation tools from Mentor Graphics or similar large-scale programs. A design project is required and students make a written and oral presentation. | Prerequisite: Graduate status.
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