Oregon State University 4 credits ECE
Combinational and sequential logic design using CMOS transistors; analysis of power consumption and logic delay of digital logic; clock design including skew, jitter, and dynamic clock energy consumption; supply voltage and power supply noise sources; dynamic voltage frequency scaling (DVFS); sub-threshold logic design and effect on energy/robustness; custom digital integrated circuit design including transistor layouts and CAD entry; CMOS scaling and the effect on process variability and power consumption.
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